Since late 1970s, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been a fundamental block of microelectronics & VLSI Design for producing highly efficient and advanced Integrated Circuits (ICs). There are many advantages of using MOSET as a fundamental logic block in ICs design like – it offers ease of scaling (more transistors in smaller area), consume less power and has simpler fabrication process.

We are well aware about the Moore’s law which states “the number of transistors per square inch on ICs doubles every year”.

Moore Made his observation in 1965 and since then the complexity of the ICs have increased many folds but his law holds true till date only because of continuous down scaling of MOSFET dimensions (size). However, MOSFET size can not be downscaled invariably, there are definite restrictions to it. As one tries to reduce the MOSFET channel length beyond a particular limit, the Gate voltage starts losing its control over the Drain current due to the onset of various Short Channel Effects (SCEs) such as threshold voltage roll-off and drain induced barrier lowering (DIBL).

In conventional MOSFET technologies, SCEs are suppressed by reducing the gate oxide thickness and increasing the channel doping concentration. But as device enters the size range of 100nm or below the reduced gate oxide thickness leads to an abrupt increase in direct tunnelling current which further leads to an unwanted increase in the standby power consumption of the MOS device. Also an increased doping concentration leads to severe speed reduction in MOS devices (International Technology Roadmap for Semiconductors, ITRS-2004).

Researcher community has well understood these issues related to Short Channel Effects (SCEs) in single gate MOSFETs. To resolve the problem and in order to keep Moore’s Law alive for many more years it is important to consider other non-classical MOSFET structures such as Double Gate MOSFETs, Triple-Gate MOSFETs, Ω-Gate MOSFETs, π-Gate MOSFETs, FINFETs, Gate All Around MOSFETs etc. for an improved device performance.

Multigate Transistors

As per International Technology Roadmap for Semiconductors (ITRS), device size scaled down to 7nm is expected around 2019. Such tiny dimensions would make the modeling of SCEs even more essential and complicated than today. Multigate structures give an advantage over single gate MOSFETs in terms of low subthreshold leakage, high ON- current, an ideal 60mV/decade slope etc., and hence an excellent control over SCEs especially in subthreshold 100nm or below regime.

Multigate MOSFETs are being considered as a major substitute to single gate devices to reach high scaling limits.

By - Dhriti Duggal - Assistant Professor (ECE) Chitkara University H.P.

References:

[1] Intel Corporation (2005). Moore’s Law: Raising the bar.
[2] H. Iwai, "Technology roadmap for 22nm and beyond," Electron Devices and Semiconductor Technology, 2009. IEDST '09. 2nd International Workshop on, Mumbai, 2009, pp. 1-4.
[3] K. J. Kuhn, "Considerations for Ultimate CMOS Scaling," IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1813-1828, July 2012.
[4] M. Alam, B. Weir and A. Silverman, "A future of function or failure? [CMOS gate oxide scaling]," IEEE Circuits and Devices Magazine, vol. 18, no. 2, pp. 42-48, March 2002.